Using VHDL in LogicWorks

In this tutorial section, we’ll look at how you can use the VHDL Language to create design descriptions and simulation models. LogicWorks allows you to create designs containing a mix of structural components (that is, schematic diagrams) and VHDL. The topics in this tutorial will get you started in creating each of these types of simulations and tying them together.

Creating a New VHDL Model

• Go to the File menu and  select the New command.
• In the list of available document types, select VHDL and then click OK.
• Go to the VHDL menu and  select Model Wizard command.

The Model Wizard allows you to crate either an independent, top level design file or a component that can be used inside other designs. Any model can be created using either VHDL or a schematic circuit diagram..

The first panel of the Model Wizard looks like this:

• In the Source selections, choose “Create a new, empty model.”
• In the Destination selection, choose “Open the new model as an independent design.”

With these selections, we are essentially creating a new, independent circuit. That is, it will not at this stage be used as a description of a component used in another design.

• Click the Next button.

The next pane allows you to choose which type of model you wish to create. In this case, we’re going to use VHDL to create a simple AND gate with one inverted input that would look like this in an equivalent logic diagram.

• Select VHDL.
• Enter a name for the new model, such as AND1INV.

Note:  Since this name will be used in the VHDL source file, you cannot use a VHDL reserved keyword or anything containing invalid characters as a name. For example, AND would not be a valid name.

• Click the Next button.

We now specify the “interface” to the model, that is, what its inputs and outputs will be. In this case, we wish to add two single-bit inputs and one single-bit output. To do this, we proceed as follows:

• Set the function to Input, if it is not already.
• Enter the name POS for the first input. The note above about names in VHDL applies also to input and output names, so you have to be sure to use something that isn’t a reserved word.
• Click the Add Single Bit button.
• Enter the name NEG, and click the Add Single Bit button again to add the second input.
• Go back to the top of the panel and change the Function selection to Output.
• Enter the name OUT1, and click the Add Single Bit button. 

The port list should look like this:

IMPORTANT: The settings in the Func column must appear as shown above!

• Click the Finish button to create the model file.

You should now see a new document window open containing text like this:

library IEEE;
use IEEE.std_logic_1164.all;

entity AND1INV is

port(
            POS: in         std_logic;
            NEG: in       std_logic;
            OUT1: out    std_logic;
);

end AND1INV;

architecture arch1 of AND1INV is

begin

–Your VHDL code defining the model goes here

end arch1;

We now have a complete VHDL description of  a component having the desired inputs and outputs, except that no code has been added to describe the actual behaviour of the device. Before we proceed, we must verify that this is a correct VHDL file.

• Go to the VHDL menu and select the Compile command.

You will notice that a new panel appears at the bottom of the screen with the compilation results. You should receive a warning that output OUT1 has not been assigned

• Locate the line that starts — Your VHDL code, and replace it with

OUT1<=POS AND NOT NEG AFTER 1NS;

Running the Simulation

• Click the Run () button to start the simulator.

You will now see the VHDL text document turn gray to indicate that it cannot be edited while the simulation is running. Now we need a method of feeding inputs into our design and checking the outputs.

• Click the I/O Panel () button. This will cause a new panel to be displayed in the results area at the bottom of the screen.

Note:  If the I/O Panel has already been used, you might need to click the I/O Panel tab in the Results Panel in order to bring it to the top.

• Check the selection list at the top of the I/O Panel. If the name IOPanelDefault.html is not already displayed, click on the list and choose the item ending with IOPanelDefault.html.

The I/O Panel is actually a special kind of Web page that can be programmed to display simulation results in many different ways. This default display show the top-level signals in the design being simulated.

• Try clicking the 0 control to set the inputs to an initial zero state and then the + controls in  the pos and neg lines to change the input values to these two inputs. Note that the circuit obeys the appropriate truth table:

pos	neg	OUT1
0	0	0
0	1	0
1	0	1
1	1	0

Displaying Timing Results

The I/O Panel is a quick way of viewing circuit inputs and outputs, but gives you no information about the relative timing of signal changes. To view the signals over time, we will use the Timing window.

• click on the Timing () button to display the timing diagram.

Since the timing diagram was actually collecting results while you were using the I/O Panel, it will display the changes that have occurred up to now:

If necessary, you can use the Zoom In and Out () buttons to adjust the resolution of the timing diagram to get a clear display.

Normally, results windows all share the same panel at the bottom of the screen. If you wish to view the Timing and I/O Panel tab, and select the Float Current Tab command:

This command places the I/O Panel in a separate, floating window so that you can view both at the same time. You could also have done this to the Timing tab, if desired.

• Now try changing the input values again, and watch the effect in the timing diagram.

Note that there is a 1-ns delay between input changes and the corresponding output change. This delay is due to the AFTER 1 NS specification in the VHDL model.

Creating a VHDL Model for a Device Symbol

We’ll now look at how we can use VHDL to describe the operation of a device that is going to be used in a LogicWorks circuit diagram. We’ll also take the opportunity to use vectors, or multibit signals.

• First, close any open circuit diagrams or VHDL files.
• Select the New command in the File menu, and then double-click on the VHDL selection.
• Select the Model Wizard command in the VHDL menu.
• For the Source selection, choose “Create a new, empty model.”
• For the Destination selection, choose “Create a new symbol with the specified model attached.” The dialog box should appear as follows:

• Click the Next button.
• Select the VHDL model type, and enter a name such as COUNT8, for the 8-bit counter device we are going to create:

• Click the Next button to view the Port Interface panel
• Set the Function to Input, if it isn’t already.
• Enter the name DIN into the name box
• Enter the number 7 as the Left Bit Number and 0 as the Right Bit Number. Click the Add Vector button. This creates an 8-bit vector with bits numbered from 7 down to 0.
• Change the name to CLK, and click the Add Single Bit button.
• Change the name to LOAD, and click the Add Single Bit button.
• Change the name to DOUT, set the Function to Output, and click the Add Vector button.
• You should now see a port list like this:

• Verify that all the port settings are correct, and then click the Next button.

The next panel allows you to specify where the pins will appear on the schematic symbol. By default, inputs will be placed on the left and outputs on the right, which should make sense for most applications. The panel appears as follows:

• If desired, move the pins to different locations on the symbol by dragging and dropping names from one box to another.
• Once you are satisfied with the pin locations, click Next button.

The last panel allows you to choose the library into which you want to save the new symbol.

• If you already have a work library open in the list, you can select it now.

Note: We do not recommend saving your own components into the libraries supplied with LogicWorks. Future upgrades to the software might replace those libraries, and you could lose your work.

• If you do not have a work library open, use the Open Lib button to open an existing library, or the New Lib button to create a new one.
• Once you have selected a library, click the Finish button. A standard Save As box will appear asking you to save the VHDL model file. This step is necessary because the name of the file will be stored with the component.
• Save the COUNT8 model file in the default location, or find any suitable folder for it.

The Model Wizard has now created a VHDL model file that describes all the inputs and outputs, but has no actual behaviour. It has also created a device symbol with entries linking it to the file. We now have two steps left: first to fill in the actual behavioural part of the VHDL model, and then to build a test circuit to make sure it works.

• Select the New command in the File menu; then choose the Circuit item. This will create a new empty circuit window on the screen.
• Locate the COUNT8 part in the parts list on the right hand side of the screen, and place one of these parts in the circuit. In case you’re not familiar with this procedure, refer to back to “Placing a Device”. You should now be looking at a circuit like this:

• Double-click on the COUNT8 device. This will open the VHDL model in a new window.
• After the line “use IEEE std_logic_1164.all,” insert the following additional use statement:

use IEEE_numeric_std.all;

This line is needed because we will be using some arithmetic data types and operations that are defined in this package.

• Locate the line near the end of the file that says something like — Your VHDL code defining the model goes here.(Remember that — indicates a comment in VHDL.) We are going to replace this line with some code that defines the operation of the 8-bit counter, as follows:

    clk_proc: process(CLK)
        variable COUNT: unsigned(7 downto 0):="00000000";
    begin
        if CLK'EVENT AND CLK ='1' then
            if LOAD ='1' then
                COUNT:=DIN;
            else COUNT:=COUNT+1;
            endif;
        endif;
        DOUT<=COUNT after 500ps;
    end process clk_proc;

NOTE: Take care when entering the fourth line in the preceding code. The item CLK’EVENT consists of the name CLK followed by an apostrophe (single quote) followed by the word EVENT. For more information on this VHDL attribute, consult a VHDL manual.

• Just to make sure you haven’t made any errors in the code, go to the VHDL menu and select the Compile command. You should get a message in the VHDL console window at the bottom of the screen indicating that the file compiled without errors. If any errors come up, fix them before proceeding. Here are some things you might want to check:
  • The input and output names (such as CLK) must exactly match the declaration at the top of the file. If you didn’t enter the names exactly the same way as in the wizard, the code won’t compile correctly.
  • VHDL is very fussy about the positions of the punctuation such as quote marks and semicolons. Make sure that all the punctuation is entered correctly.
  • =, <=, and := can all be reads as “equal” to us, but they have different meanings! Make sure that all the instances of these sequences are entered properly.
• Once the file compiles correctly, close the COUNT8 document window. You should now be again looking at the circuit containing the COUNT8 symbol. The system description is now complete, so we just have to test it.

Although we could use the I/O Panel as we did in the previous tutorial, we’ll take a different approach this time and add circuitry to the diagram in order to test the new device.

• Click and hold at the end of the DOUT pin, and extend the bus line as shown.

• Right-click anywhere along the bus line and select the Breakout command. This will display the following box:

• This box should already show the signal range DOUT_0,,DOUT_7, which means that all the individual bits from 0 to 7 will be split out of the bus. Click the OK button.
• Place the breakout symbol so that it connects to the DOUT bus as shown here:

• Next locate the Hex Display device in the parts list, and place one so that it connects to the bottom four pins on the breakout. Repeat this step to place a second HexDisplay device for the top four pins. The circuit diagram should now appears as follows:

• Using a similar procedure, extend the DIN bus to the left, right click on it to select the Breakout command, and place the breakout. You may need to use the arrow keys on the keyboard to orient the symbol as shown in the next diagram.
• Locate the Hex Keyboard device in the parts list. Double-click on it, and move it into the circuit area. You may need to use the arrow keys on the keyboard to orient it the right way to attach to the breakout.

• Pace a Binary Switch device and wire it to the LOAD input; then place a Clock device and connect it to the CLK pin. You should now have a diagram like this one:

To make it easier to display the results let’s apply names to a couple of the signals that we will want to observe. Select the Text() tool, and then click on the bus line coming out of the DOUT pin. Enter the name DOUT, and press Enter on the keyboard. Use the same procedure to apply the name CLK to the output of the Clock device.You may want to move some of the devices around to make room for  the names.

Here is our final circuit:

• This would be a good time to save the design, in case we want to come back to it later. Select the Save As command in the File menu, and save the design as COUNT8 test or any other name that suits you.
• If it is not checked already, select the Show Values command in the Simulation menu in order to show the values of the signal on the circuit diagram.
• Click the Run () button to start the simulator.

You should now see the signal value displays change and the time indicator in the toolbar start to advance. Time is advancing because of the Clock device we placed in the circuit. This device generates a continuous sequence of 0-to-1 value changes at its output, regardless of what else is happening in the circuit.

• Click on the LOAD switch to change its value to 1.
• Click on the hex keypads at the inputs, and observe that the input values are being transferred to the output on the clock.
• If it is not already displayed, show the timing diagram by clicking on the Show Timing() button or by clicking on its tab in the results window. If desired, you can change the resolution of the timing diagram by using the Zoom In and Out() tools.

Using a LogicWorks Symbol in a VHDL Design

In this tutorial, we will create a design by using VHDL to create the top-level description and having it refer to LogicWorks symbols as building blocks. This is the reverse of the situation described in the previous tutorial.

Important: The VHDL language has more severe restrictions on names than the general LogicWorks program. In order for a symbol to be usable as a device model within a VHDL description, the name of the library itself, the name of the symbol and the names of all pins on the symbol must meet VHDL naming requirements. In general, this means that names cannot contain any spaces or special characters. Most of the libraries provided with LogicWorks do not meet these requirements, so you must either use the specific libraries provided for this purpose or create your own versions of libraries that have appropriate names.

• Select the New command in the File menu, and then click on the Model Wizard in the Simulation menu.
• In the Source selection, choose “Create a new, empty model.”
• In the Destination selection choose “Open the new model as an independent design.”
• Click the Next button
• Select the VHDL model type.
• Enter the name FULL_ADDER for the new model.
• Click the Next button.

We now specify the “interface” to the model, that is, what its inputs and outputs will be. In this case, we wish to add three single-bit inputs and two single-bit outputs. To do this, we proceed as follows:

• Set the function to Input, if it is not already.
• Enter the name c_in for the first input, and click the Add Single Bit button.
• Repeat the foregoing step for inputs named a and b.
• Go back to the top of the panel and change the Function selection to OutPut.
• Add output bits sum and c_out.

The port list should now look like this:

• Click the Finish button to create the model file.

You should now see a new document window open containing text like this:

To make this code into a complete description, we will add component instantiation statements that refer to LogicWorks gate symbols stored in libraries.

• In the VHDL file, locate the use statement close to the top of the file. After this line, insert the following additional statements:

    library Libs;
    use Libs .VHDLPrims.all;

These statements tell VHDL where to find the components to which we will be referring. The name, in this case VHDLPrims, must refer to a library that is already open in the LogicWorks parts palette.

• Locate the architecture statement in the file. On the next line, insert the following declaration:

This line creates some intermediate signals that will be part of our model.

• Find the comment line starting with — Your VHDL code that appears near the end of the file. Replace this comment with the following lines:

        G1 : xor_3 port map(INA=>c_in, INB=>a, INC=>b, Y=>sum);
        G2 :and_2  port map(INA=>c_in, INB=>a, Y=>s1);
        G3 :and_2  port map(INA=>a, INB=>b, Y=>s2);
        G4 :and_2  port map(INA=>c_in, INB=>b, Y=>s3);
        G5 :or_3  port map(INA=>s1, INB=>s2, INC=>s3,  Y=>c_out);

The xor_3, and_2, and or_3 components are all items that will be fetched from the LogicWorks library VHDLPrims. The component names and pin names must exactly match those defined on the symbol.

• Use the Save or Save As command 
• to save your file for safekeeping.
• Click the Run() button to start the simulator. If any compilation errors occur, they will be reported in the VHDL console window, otherwise, the VHDL window will go gray to indicate that it is locked while the simulation is running.

• Click the  I/O Panel () button. This will display a new panel in the results area at the bottom of the screen.
• Try entering values for the a,b, and c_in inputs, and verify that the model is working as expected. Here is the truth table for a full adder that our model should follow:

NOTE:  The delay values used by the LogicWorks symbols are determined by settings that were supplied when the symbols were created. There is no way of changing the delays in the symbols themselves from the VHDL file., although you could apply additional delays to the signals.

This ends the tutorial on VHDL.

 The next tutorial is Creating a Device Symbol.