Structural Simulation

This section of the tutorial will provide you with a closer look at the integrated digital simulator in LogicWorks, including the following topics:

  • types of devices simulated;
  • controlling the simulation
  • representation of time and signal values;
  • using the trigger;
  • using the signal probe;

Logic States

  • Create a new circuit, using the New command in the File menu.
  • Create the following partial circuit, using the Buffer-1 O.C. and the Binary Probe device:

LogicWorks uses a total of 13 different logic values for signals in order to handle different drive levels and unknown situations. The probe will display an X for any of the  possible “Don’t Know” states. In this case, the X results from the fact that the device input is unconnected.

  • Add a Binary Switch device to the input of the buffer as shown.
  • Click on the switch a couple of times, and note that the buffer output alternates between the 0 and Z state.

The Z value indicates a high-impedance or undriven line. Multiple open collector or three-state devices can drive a line to simulate bus or wired-AND logic.

Circuits with Feedback

  • Click on the Buffer device, and use the Duplicate command in the Edit Menu to create another one as shown.
  • Add a pull-up resistor (using the Resistor and +5V symbols) and an inverter (NOT in the Simulation library), and wire them as shown above.
  • Click on the switch, and notice the oscillation that occurs due to the feedback in this circuit.
  • Name the output  signal CLK so that it shows in the Timing window.

Using the Signal Probe

  • Click on the Signal Probe tool in the toolbar.
  • Click the tip of the Signal Probe tool along any signal line, as demonstrated in the following diagram:

It will show the current value of the signal as the simulation progresses.

You can also use this tool to enter new signal values by typing 0 or 1 on the keyboard while the left mouse button is pressed. Stuck-at, unknown, and high-impedance levels can also be inserted.

Time Values

LogicWorks uses integers to represent simulated time values.  Most devices included with LogicWorks default to a delay of 1 ns (nano second, or 10-9 seconds).

LogicWorks uses an event-driven simulator, meaning that device values are recalculated only when an input change occurs. Thus, the speed at which the simulation occurs does not depend on delay or other time values in the circuit.

Primitive Devices

  • Click on the inverter (NOT) device with the arrow tool in order to select it.
  • Select the Simulation Params command in the Simulation menu. The following windows will appear:

The inverter is classified as a primitive device, since its simulation function is built into the program. Primitive devices have a single time value that defines the delay from any input pin to any output pin for any transition.  More complex models can be implemented by using pin delays or by building sub-circuit devices out of the existing primitives.

  • Click in the delay value box, and change the number to 5 ns; then click on the OK button. Notice the effect this delay change has on the period of the oscillation in this circuit, as displayed in the timing diagram. 

Power and Ground Signals

  • Select a 74_164 4-bit counter device from th 7400 library, and place it in the circuit diagram as shown.
  • Using the text tool, as described previously, add the names “CLK” and “ENABLE”.
  • Place +5V and Ground symbols as shown to permanently fix these signals to high and low levels, respectively.

Sub-circuit Devices

  • Add the names D0 to D3 using the following procedure:
  • Name the least significant counter output D0 using the usual technique.
  • Hold down the CTRL key on the keyboard while you click on the each higher pin in turn. Make sure you click only at the very end of the pin. This will automatically place sequential numbers on the lines clicked.

Notice that the traces D0 to D3 in the Timing window will show unknown values, because the counter has never been cleared into a known state.

  • Press the Clear X () button in the Simulator toolbar. This resets all storage elements to the zero state and clears unknown lines.
  • Reactivate the arrow cursor.
  • Click on the 161 device to select it, and then select the Sim Params command in the Simulation menu.

The 161 counter is a sub-circuit device, meaning that its logic function is implemented using a combination of LogicWorks primitive devices. Because of this, the overall delay for the device cannot be adjusted by simply changing one parameter. Two methods are available for modifying delays in sub-circuit devices and are discussed in the upcoming sections.

  • Click the OK button on the warning box.
  • Right-click on the 161 device.
  • In the pop-up menu, select the Device Info command.
  • Click on the “Lock Opening Subcircuit” check box to turn it off.
  • Click on the OK button to close the dialog. 
  • Double-click on the 161 device to open its internal circuit. A new window will open showing the internal circuit of this device, which will appear as follows:

Notice how you can use the Signal Probe tool, the Parameters command, and all the drawing tools to view and modify this internal circuit. If you modify this circuit, all devices of the same type in this design will be equally affected.

Pin  Delays

  • Using the arrow cursor, click midway along the QA output pin on the 161 device to select it:
  • Using the arrow cursor, click midway along the QA output pin on the 161 device to select it:
  •  Select the Simulation Params command from the Simulation menu.

LogicWorks allows you to set a delay on an individual pin on a primitive or sub-circuit device. The logical effect is the same as if you had inserted a buffer device with the specified delay in series with the pin. Pins always have a default delay of Zero.

  • Set the pin delay to 2 NS and click OK.

Notice the effect this step has on the D0 trace in the Timing window.

Pin delays can be used to customize  path delays in sub-circuit devices without opening and modifying their internal delays. Setting pin delays on a sub-circuit device affects only the single device modified., whereas changing internal delays of primitive devices will affect all copies of the same type of device.

Moving Timing Traces

  • Click and vertically drag the name CLK in the Timing window to reposition it relative to the other traces:

You can reposition any group of traces for ease in making timing comparisons. Any number of traces can be moved at once by holding the SHIFT key while clicking on the trace names.

Group Timing Traces

  • Click on the name D0 in the Timing window. Hold the SHIFT key down while you click on the names D1, D2, and D3 so that they are all selected.
  • Click the right mouse button on any of the four selected names.
  • In the pop-up menu, select the Group command.

You will now see that the four traces D0 to D3 collapse into a single grouped trace showing their combined value in hexadecimal.

The same pop-up menu can be used to ungroup the signals again or to set the signal order used to create the hexadecimal value.

Note that the grouped trace has double vertical bars on some values. This is due to the delay we inserted in the QA output pin. If you set the pin delay back to zero, the double bars will revert back to single bars.

NOTE: The hexadecimal value of a grouped signal will be displayed only if there is sufficient space between the signal changes to display the text. You can use the zoom In and Zoom Out buttons () to change the scale factor in order to see the values.

Using the Trigger

  • Click on the Trigger button () in the Simulator toolbar.

The trigger mechanism allows you to detect various timing and signal-state conditions.

  • Type the name CLK in the Names box.
  • Type the value 1 in the Value box.
  • Select the Reference Line option. The dialog should not appear as follows:
  • Click the OK button.

You will now see that a reference line is drawn on the Timing window each time the CLK signal changes to a 1 state. You can also enter ranges of signal names(e.g. D7..0) and corresponding hexadecimal values (e.g. 7A) into these boxes in order to match more complex  events.

This completes the tutorial section on  structural simulation.

Tutorial – Structural Simulation The next tutorial is Using VHDL in LogicWorks.