Home Forums LogicWorks Windows Circuits Schematic diagram with VHDL behavioural blocks for a lottery 'lucky-dip' machine

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    This design makes use of a counter that continuously counts from 0x01 to 0x49 in binary coded decimal, these being the numbers used by the UK National Lottery. A behavioural VHDL block (lottery4) samples the counter output whenever the ‘next’ button is toggled and compares the new number with those already stored within an internal memory array (avoids duplicate numbers). Once six numbers have been chosen, the ‘six’ output goes high to indicate this and the numbers are then continuously scrolled through on the 7-segment displays until the ‘reset’ input is asserted. Assuming the 1 to 49 counter is counting at high frequency, the numbers should be random. This design demonstrates the use of the array type in VHDL along with behavioural modelling of a synchronous sequential design.

    Donated by Ian Elliott

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